Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure

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United States of America Patent

PATENT NO 7135408
SERIAL NO

10283862

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A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to initially deposit a thin underlying, first component of the barrier layer, while an atomic layer deposition (ALD), procedure is then employed for deposition of an overlying second barrier layer component. The underlying, thin barrier layer component obtained via PVD procedures is comprised with the desired properties needed to interface the porous, low k layer, while the overlying barrier layer component obtained via ALD procedures exhibits excellent thickness uniformity.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jang, Syun-Ming Hsin-Chu, TW 374 6646
Wu, Zhen-Cheng Hsinchu, TW 62 665

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