Semiconductor devices including a gate isolation structure and a gate capping layer including different materials from each other
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United States of America Patent
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Dec 7, 2021
Grant Date -
Feb 4, 2021
app pub date -
Mar 18, 2020
filing date -
Jul 30, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.
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