Timing verifying method
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United States of America Patent
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Jan 14, 2003
Grant Date -
Oct 25, 2001
app pub date -
Apr 20, 2001
filing date -
Apr 21, 2000
priority date (Note) -
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Abstract
In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.
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