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Abstract

The present invention discloses a method, apparatus, and article of manufacture for wire width planning and performance optimization for very large scale integration (VLSI) interconnects. Two simplified wire sizing schemes are described for the VLSI interconnect, namely a single-width sizing (1-WS) or a two-width sizing (2-WS). These simplified wire sizing schemes have near optimal performance as compared to more complex wire sizing schemes with many or even an infinite number of wire widths. A wire width planning method is then described to determine a small set of globally optimal wire widths for the VLSI interconnects in a range of lengths. It is concluded that near optimal interconnect performance can be achieved by using such pre-designed, limited number of wire widths (usually two-width design is adequate). The layout for the VLSI interconnects is then generated and optimized using the limited number of wire widths.

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First Claim