WAK devices in SRAM cells for improving VCCMIN
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United States of America Patent
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Jun 8, 2010
Grant Date -
Aug 20, 2009
app pub date -
Feb 20, 2008
filing date -
Feb 20, 2008
priority date (Note) -
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Abstract
A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.
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