Programmable processor execution rate controller
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United States of America Patent
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Jun 8, 1999
Grant Date -
N/A
app pub date -
Dec 27, 1996
filing date -
Dec 27, 1996
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Abstract
A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying 'cycle-slip' data for each instruction type in the instruction set. This cycle-slip data is used to force the instruction processor to idle for the specified number of execution cycles during the execution of the associated instruction type, thereby slowing down the rate of execution. Allowing rate control data to be unique for each instruction type allows temporary fixes to be implemented when timing-related hardware problems are discovered during system test. If desired, a uniform number of cycle slips can be imposed on all instructions so that the overall rate of the instruction processor is tailored to match the execution rate of slower peripheral devices.
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