Buffer circuit with current limiting
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United States of America Patent
Stats
-
Sep 18, 2007
Grant Date -
Oct 5, 2006
app pub date -
Mar 31, 2005
filing date -
Mar 31, 2005
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.
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