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Abstract

A massively parallel vector computer comprises a set of vector processing nodes, each node including a main processor for controlling access to a random access memory through an internal bus and a set of ports for interfacing external busses to the internal bus. The external busses interconnect pairs of nodes to form a network through which data may be transmitted from the random access memory in any one node to the random access memory in any other node in the network. Each vector processing node also includes a vector memory accessed through a local bus, the local and internal busses communicating via an additional port controlled by the main processor. A vector processor within each node performs operations on vectors stored in the vector memory and stores the results in the vector memory. A peripheral processing network comprises a set of peripheral processing nodes interconnected via further busses, and wherein selected peripheral processing nodes are coupled to selected vector processing nodes. The peripheral processing nodes are adapted to transmit data to and receive data from peripheral devices.

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