Two terminal memory array having reference cells
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United States of America Patent
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Jun 5, 2007
Grant Date -
Nov 2, 2006
app pub date -
Jun 29, 2006
filing date -
Jul 20, 2004
priority date (Note) -
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Abstract
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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