Fiber attach enabled wafer level fanout

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United States of America Patent

PATENT NO 11822128
SERIAL NO

17516602

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Abstract

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A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

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Patent Owner(s)

  • AYAR LABS, INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ardalan, Shahab Santa Clara, US 9 46
Davenport, Michael Santa Barbara, US 36 162
Meade, Roy Edward Lafayette, US 47 113

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