ESD protection circuit for radio frequency input/output terminals in an integrated circuit
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United States of America Patent
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May 29, 2007
Grant Date -
Oct 2, 2003
app pub date -
Oct 31, 2002
filing date -
Mar 28, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit comprises an ESD protection circuit including an inductor coupled between an input terminal and a ground terminal at which an RF signal is applied. The inductor is designed so as to provide a sufficient current capability required in typical ESD events. Moreover, the inductance of the inductor is selected to define, in combination with any parasitic capacitance present, a resonance tank with a resonant frequency that is matched to the RF signal. Accordingly, the operating frequency of the integrated circuit is not limited by the ESD protection circuit. In a further embodiment, an output terminal is ESD protected by an inductor that is coupled to an auxiliary voltage serving to bias an output transistor. Moreover, clamping elements, such as diodes, are provided between the auxiliary voltage and the supply voltage and between the auxiliary voltage and ground potential.
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