Semiconductor device and manufacturing method thereof
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United States of America Patent
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Jul 19, 2022
Grant Date -
Jun 11, 2020
app pub date -
Feb 10, 2020
filing date -
Jan 7, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.
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