Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

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United States of America Patent

PATENT NO 11966334
APP PUB NO 20210209023A1
SERIAL NO

17146440

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gabor, Ron Herzliya, IL 71 564
Yanover, Igor Yokneam Illit, IL 41 200

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