Dynamic packet processor architecture
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United States of America Patent
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May 4, 2004
Grant Date -
Aug 15, 2002
app pub date -
Mar 9, 2001
filing date -
Feb 14, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
The packet processor system has a port for receiving packets from a first network. A line interface unit is connected to the port for determining the types of packets that are received by the port. A generic pipeline stage assembly is connected to the line interface unit and includes a plurality of generic pipeline stages each having a request engine for sending lookup requests to a lookup engine and a modifier engine for receiving lookup results from the lookup engine. A packet memory is connected to a last generic pipeline stage of the generic pipeline stage assembly and an output line interface unit is connected to the packet memory and a second network.
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