Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

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United States of America Patent

PATENT NO 7198993
APP PUB NO 20060128074A1
SERIAL NO

11010849

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Abstract

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A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).

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Patent Owner(s)

  • TEXAS INSTRUMENTS INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barna, Gabriel G Richardson, TX 12 397
Faynot, Olivier Alain Seyssinet, FR 4 16
Tigelaar, Howard L Allen, TX 54 1631

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