Semiconductor memory device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6130461
SERIAL NO

09291042

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Abstract

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A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Oowaki, Yukihito Yokohama, JP 80 1600
Yoshida, Masako Yokohama, JP 41 373
Yoshimi, Makoto Tokyo, JP 27 1013

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