Chip-type sensor against ESD and stress damages and contamination interference
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United States of America Patent
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Jul 4, 2006
Grant Date -
Oct 20, 2005
app pub date -
Apr 16, 2004
filing date -
Apr 16, 2004
priority date (Note) -
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Abstract
A chip-type sensor against ESD and stress damages and contamination interference includes a substrate structure and a protection layer covering over the substrate structure. The protection layer includes, from bottom to top, a first layer for providing a first stress against the substrate structure, a second layer for providing a second stress against the substrate structure, and a third layer for providing a third stress against the substrate structure. The first stress and the third stress belong to one of a tensile stress and a compressive stress, and the second stress belongs to the other of the tensile stress and the compressive stress.
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