Semiconductor integrated circuit and layout designing method of the same
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United States of America Patent
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Dec 22, 2009
Grant Date -
Mar 15, 2007
app pub date -
Sep 15, 2006
filing date -
Sep 15, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor integrated circuit of the present invention comprises a hard macro and a plurality of wirings connected to the hard macro. The hard macro comprises a hard macro main body, and a plurality of pins with a minimum pin width based on a design rule of the semiconductor integrated circuit, which is connected to the wirings. Each of the pins is arranged in a vicinity of the peripheral edge of the hard macro main body with a minimum isolated space based on the design rule provided therebetween along a direction crossing with a width direction of the peripheral edge. The wirings are arranged obliquely along a direction crossing with a perpendicular direction of the peripheral edge.
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