Memory packages having stair step interconnection layers
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United States of America Patent
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Dec 16, 2008
Grant Date -
Nov 2, 2006
app pub date -
May 2, 2006
filing date -
Nov 17, 2003
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.
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