“Read after erase” method for catching single word line “slow to erase” signature in nonvolatile memory structures

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United States of America Patent

PATENT NO 11545225
SERIAL NO

17356823

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Abstract

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A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amin, Parth Fremont, US 27 64
Khandelwal, Anubhav San Jose, US 32 710

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