Semiconductor integrated circuit and test method thereof
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United States of America Patent
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Jul 23, 2019
Grant Date -
Sep 27, 2018
app pub date -
May 25, 2018
filing date -
Sep 11, 2015
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.
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