Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces
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United States of America Patent
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Mar 9, 2010
Grant Date -
Mar 19, 2009
app pub date -
Nov 19, 2008
filing date -
Jan 14, 2005
priority date (Note) -
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Abstract
Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.
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