Semiconductor device including source/drain contact having height below gate stack

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United States of America Patent

PATENT NO 11862623
APP PUB NO 20230187434A1
SERIAL NO

18167651

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Abstract

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A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chih-Liang Hsinchu, TW 259 1284
Chen, Chun-Kuang Hsinchu County, TW 126 678
Chen, Shun-Li Tainan, TW 13 19
Lai, Chih-Ming Hsinchu, TW 471 10367
Liu, Ru-Gun Hsinchu County, TW 388 5855
Peng, Shih-Wei Hsinchu, TW 172 219
Sio, Kam-Tou Hsinchu County, TW 124 460
Tzeng, Jiann-Tyng Hsinchu, TW 292 779
Young, Charles Chew-Yuen Cupertino, US 124 378

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