Pipelined analog-to-digital converter with unequal work timing
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United States of America Patent
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Aug 23, 2005
Grant Date -
N/A
app pub date -
Nov 8, 2004
filing date -
Nov 8, 2004
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Abstract
A pipelined analog-to-digital converter with unequal work timing comprising several transfer circuits and a decoder is provided. Each transfer circuit includes an analog-to-digital sub-converter, a multiply digital-to-analog converter, a subtractor and an amplifier. The operation time of the analog-to-digital sub-converter is in a sampling time and the operation time of the multiply digital-to-analog converter, the subtractor and the amplifier is in an amplifying time. The amplifying time is longer than the sampling time. The decoder receives the digital bit signals produced by the analog-to-digital sub-converter of the transfer circuit to produce digital signals.
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