Arrangements detecting reset PCI express bus in PCI express path, and disabling use of PCI express device
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United States of America Patent
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Jan 29, 2013
Grant Date -
Jun 7, 2012
app pub date -
Feb 13, 2012
filing date -
Mar 26, 2009
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A root port connection functioning as a PCI express bridge, and having a PCI express path constituting a PCI express tree having a PCI express device or switch; when detecting a failure on a PCI express path, a PCI express device or switch transmits a failure signal; the root port transmits an SMI responsive to the failure signal; the CPU executes the BIOS responsive to the SMI; the BIOS collects a log of the PCI express path where failure is detected, analyzes the collected log to judge failure type, and upon a fatal failure on the PCI express path, resets the PCI express tree downstream of the root port that received the failure signal, and upon a non-fatal failure on the PCI express path, resets the PCI express device in which the failure occurred; and the CPU closes the reset PCI express device by executing the device driver.
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