Method and system for synchronizing video information derived from an asynchronously sampled video signal
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United States of America Patent
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Mar 3, 2009
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N/A
app pub date -
Mar 17, 2005
filing date -
Oct 13, 2004
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Abstract
A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.
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