Importance

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Abstract

For use in a microprocessor on a single semiconductor chip, a circuit responsive to first and second non-overlapping time signals for removing timed delay in a first data line. A first enhancement-type field effect device has its drain coupled to the first data line and its gate providing an input for the first timing signal. A second enhancement-type field effect device has its drain coupled to the source of the first device and its source coupled to a source voltage. The source voltage is at ground potential. A third enhancement field effect device has its drain coupled to the first data line, its source coupled to the gate of the second device, and its gate providing an input for the second timing signal.

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First Claim