Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1-xGe.sub.x as sacrificial material
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United States of America Patent
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Apr 29, 2008
Grant Date -
Jan 19, 2006
app pub date -
Jul 13, 2004
filing date -
Jul 13, 2004
priority date (Note) -
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Abstract
A method of forming a metal gate in a wafer. PolySi.sub.1-xGe.sub.x and polysilicon are used to form a tapered groove. Gate oxide, PolySi.sub.1-xGe.sub.x, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi.sub.1-xGe.sub.x, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS.sub.1-xGe.sub.x, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi.sub.1-xGe.sub.x, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
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