METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR USING CLOCK SIGNAL CONTROL
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United States of America Patent
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Jun 19, 2007
Grant Date -
Jun 28, 2007
app pub date -
Dec 22, 2005
filing date -
Dec 22, 2005
priority date (Note) -
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Abstract
Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
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