DC offset correction circuit utilizing switched capacitor differential integrator
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United States of America Patent
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-
Dec 30, 1986
Issued Date -
N/A
app pub date -
May 28, 1985
filing date -
Oct 13, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit employing a differential integrator and switched capacitor network to provide auto-zeroing. The differential integrator utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier provides voltage division of differential reference signals which determine the amount of DC offset. The amplifier then integrates the reference signals to a predetermined time constant, wherein the average voltage of the output of the integrator is used to provide auto-correction of the DC offset. A second switched capacitor voltage divider network and a second differential integrator cascaded to the first circuit provides a second time constant for fine-tuning the auto-correction signal.
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