Apparatus and method for testing memory in a microprocessor
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United States of America Patent
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Dec 10, 2002
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N/A
app pub date -
Oct 3, 2001
filing date -
Apr 26, 1999
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Abstract
An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.
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