Extended drain resurf lateral DMOS devices
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United States of America Patent
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Dec 17, 1996
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Apr 8, 1994
priority date (Note) -
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Abstract
A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.
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