Importance

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Abstract

A latch circuit having reduced propagation delay and set-up and hold times comprises at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit. A first input transistor device is coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices, and a second input transistor device is coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices. The first and second input transistor devices are adapted for application of respective uncomplemented and complemented inputs thereto during an initialization mode of the latch circuit. Uncomplemented and complemented output signals are generated at corresponding output terminals associated with the set of cross-coupled transistor devices during an evaluation mode of the latch circuit. The latch circuit may be implemented as a master in a master-slave configuration having additional slave circuitry so as to provide a tradeoff between operating speed and a desired set-up and hold time window.

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First Claim