Programmable mechanism for delayed synchronous data reception
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United States of America Patent
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Jun 10, 2014
Grant Date -
Dec 27, 2012
app pub date -
Jun 21, 2011
filing date -
Jun 21, 2011
priority date (Note) -
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Abstract
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.
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