Current delivery and spike mitigation in a memory cell array

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11322546
APP PUB NO 20190043923A1
SERIAL NO

16145084

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Abstract

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A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.

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Patent Owner(s)

  • INTEL CORP.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahmed, Shafqat San Jose, US 32 300
Pangal, Kiran Fremont, US 91 848

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