Memory device
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United States of America Patent
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-
Jul 30, 1991
Grant Date -
N/A
app pub date -
Nov 1, 1989
filing date -
Nov 1, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A compact, high speed EEPROM is disclosed. The design features mirror-image pairs of cells with a common junction buried under a thick oxide. The oxide also supports a portion of the control and floating gates. A single erase gate, also above the oxide, is capable of erasing two rows of cells at once. Each cell also has a second junction which contacts the semiconductor substrate surface. The second junction has a conductive landing pad which facilitates small cell size.
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