Importance

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Abstract

A system is disclosed for merging data from two separate registers at different locations in a computer system. A floppy drive controller is provided as part of a companion chip located separately from an IDE drive controller. Both controllers include a data register with the same address to make the system compatible with prior BIOS programs. The register in the floppy controller includes a DSK CHG bit as bit D7 of a direct input register (DIR), which is obtained from the DSK CHG# signal from the floppy drive. In the present invention, the DSK CHG# signal from the floppy drive is connected directly to the bus interface unit (BIU) of the integrated processor. The processor merges this signal with data bits D0-D6 of the IDE controller by determining the location of the IDE controller from the Address Control Register (ACR), which is determined during system initialization. The floppy drive controller also is programmed during system initialization not to respond to an access to address value 3F7h by programming a configuration register in the controller. The BIU determines whether it should merge the data or whether the IDE controller will merge the data by checking the status of a MERGE bit in the ISACFG register, which also is configured during system initialization.

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First Claim