Importance

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Abstract

An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUXl, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.

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First Claim