Latency normalization by balancing early and late clocks

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7324403
APP PUB NO 20060067155A1
SERIAL NO

10949053

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rashid, Mamun Ur Folsom, CA 14 121
Salmon, Joe Placerville, CA 10 109
To, Hing Yan Cupertino, CA 9 81

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation