Method for fabricating a high-bias semiconductor device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 12, 2000
Grant Date -
N/A
app pub date -
Nov 20, 1998
filing date -
Nov 20, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for fabricating an improved structure of a high-bias device includes forming multiple doped wells between source/drain regions and a P-type substrate. The doped wells have an increasing order of dopant density from the P-type substrate for the P-type dopant or from a first N-type well for an N-type dopant. The doped multiple wells enclose the source/drain regions so that the source/drain regions do not directly contact with the substrate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully