Interconnect dielectric tuning
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United States of America Patent
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Aug 21, 2007
Grant Date -
N/A
app pub date -
May 22, 2006
filing date -
Aug 10, 2004
priority date (Note) -
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Abstract
An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
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