Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit

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United States of America Patent

PATENT NO 11799481
SERIAL NO

17549316

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Abstract

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The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

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Patent Owner(s)

  • SK HYNIX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choi, Eun Ji Icheon-si, KR 15 11
Hwang, Jin Ha Icheon-si, KR 52 172
Jeong, Yo Han Icheon-si, KR 30 27

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