Importance

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Abstract

A data processing apparatus comprises a program counter for designating the address of a microinstruction to be read. A decoder receives the microinstruction stored in the address designated by the program counter and generates at least a first selection signal, a second selection signal, a first register address signal and a number-of-counter-selection signal. A first counter receives a first timing signal to count the first timing signal when the first selection signal is active so that the first counter generates a second register address signal incremented at each occurrence of the first timing signal. A multiplexer receives the first and second register address signals to select and output the second register address when the first selection signal is active. A register group including a plurality of registers is responsive to the first timing signal to latch the output of the multiplexer so as to select a register designated by the output of the multiplexer. A second counter receives the first timing signal to count the first timing signal when the second selection signal is active. A comparator is provided to compare the count content of the second counter with the number-of-counter-selection signal and to reset the second counter when the content of the second counter becomes consistent with the number-of-counter-selection signal, with the result that the comparator itself generates one step-up signal to the program counter.

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First Claim