CMOS device integration for low external resistance
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United States of America Patent
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Mar 13, 2007
Grant Date -
Sep 30, 2004
app pub date -
Jan 23, 2004
filing date -
Mar 28, 2003
priority date (Note) -
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Abstract
The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first suicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.
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