Methods for fabricating sub-resolution alignment marks on semiconductor structures

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United States of America Patent

PATENT NO 8585915
APP PUB NO 20090110878A1
SERIAL NO

11926619

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Abstract

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A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pratt, David S Meridian, US 27 597
Sulfridge, Marc A Boise, US 2 31

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