Method of etching a layer in a semiconductor device
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United States of America Patent
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-
Mar 13, 2001
Grant Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1997
priority date (Note) -
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Abstract
In the process of simultaneously etching a polysilicon layer in a groove of a memory cell section and a polysilicon layer in a peripheral circuit section, a Cl.sub.2 /HBr-based gas is used as a first etching step, and this etching is performed until polysilicon in the peripheral section is removed. Next, the gas is switched to a C1.sub.2 /HBr/O.sub.2 -based gas to remove an etched particulate resist film having accumulated in the groove. As a final step, the polysilicon layer remaining in the groove is etched with a HBr/O.sub.2 -based gas having a high selectivity ratio against an oxide film.
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