Scanner overlay correction system and method
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United States of America Patent
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Sep 13, 2016
Grant Date -
Jun 18, 2015
app pub date -
Dec 30, 2014
filing date -
Dec 17, 2012
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Abstract
A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.
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