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Abstract

A method of forming a semiconductor with n-channel and p-channel transistors with optimum gate to drain overlap capacitances for each of the different types of transistors, uses differential spacing on gate electrodes for the respective transistors. A first offset spacer is formed on the gate electrode and an n-channel extension implant is performed to create source/drain extensions for the n-channel transistors spaced an optimum distance away from the gate electrodes. Second offset spacers are formed on the first offset spacers, and a p-channel source/drain extension implant is formed to create source/drain extensions for the p-channel transistors. The increased spacing of the source/drain extension implants away from the gate electrodes in the p-channel transistors accounts for the faster diffusion of the p-type dopants in comparison to the n-type dopants.

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First Claim