Internal voltage generation circuit capable of stably generating internal voltage with low power consumption
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United States of America Patent
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-
Jul 11, 2000
Grant Date -
N/A
app pub date -
May 24, 1999
filing date -
Nov 19, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A gate voltage of output driving MOS transistor is adjusted through a negative feedback circuit. The negative feedback circuit suppresses variations in gate voltage of the output MOS transistor by the feedback loop. A gate length of the output driving MOS transistor is set substantially equal to a gate length of a transistor included in the negative feedback circuit. The power supply voltage dependency of the output voltage is canceled out. The output voltage is represented by the difference between threshold voltage of a biasing transistor in the negative feedback circuit and the threshold voltage of the output driving MOS transistor. Output voltage is stably generated at a fixed level without being influenced by operation environment and fluctuation in manufacturing parameters.
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