Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 21, 1998
Grant Date -
N/A
app pub date -
Dec 19, 1995
filing date -
Dec 19, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multithreaded processor includes an instruction pipelined unit 140 and a register file 120 composed of a plurality of register banks 130. The register file 120 is coupled to an external memory 190 through register frame load/store lines 121, so that a register frame, which is defined as a content stored in one register bank 130, can be loaded and stored in bundle. When a thread parallel start instruction and a thread sequential start instruction are executed, the register frames are saved through the load/store lines 121. When a thread end instruction and a thread return instruction are executed, the register frames are restored through the load/store lines 121.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully